Embodiments of the inventive concepts relate to a semiconductor memory device, and more particularly, to a semiconductor memory device with a stacked chip structure in which several dies are stacked.
A stacked chip structure such as high bandwidth memory (hereinafter referred to as “HBM”) may provide the memory device with great capacity and high-speed operation.
The HBM may be implemented with a plurality of memory dies stacked on a buffer die (or a base die). The buffer die plays a role of a logic circuit to control the memory dies. Here, the buffer die and the memory dies are respectively connected by a through silicon via (hereinafter referred to as “TSV”). The TSV transfers data and control signals between the memory devices and the buffer die.
A 2.5D chip structure and a 3D chip structure have been known as the form of the stacked chip structure. The 2.5D chip structure is a chip structure in which the HBM and a host are connected to each other by means of an interposer instead of a printed circuit board (PCB) for electrical connection. The 3D chip structure is a chip structure in which the HBM is stacked on the host such that the host and the HBM are directly connected with an interposer.
An error may occur during data read operation due to a malfunction of the HBM or due to a transmission signal noise of the stacked chip structure. For correcting the error, the chip needs to identify whether the error is an error (or a memory die-based error) occurring within a memory die or whether the error is a transmission error due to noise.
Here, the transmission error which occurs due to noise when data is transmitted through the TSV is regarded as one type of soft data failure.